1. Field of Invention
The present invention relates to a method for manufacturing semiconductor devices. More particularly, the present invention relates to a method using self-aligned process to increase device-packing density.
2. Description of Related Art
In integrated circuit (IC) design, much effort is dedicated to improving the performance and complexity of the IC, while increasing the packing density of the circuit. Packing density is the number of devices capable of being packed onto a given chip area, where in recent years semiconductor devices are being fabricated with features less than a quarter of a micron across.
Increasing circuit density has not only improved the complexity and performance of ICs but has also provided lower cost parts to the consumer. An IC fabrication facility can cost hundreds of millions, or even billions, of dollars. Each fabrication facility will have a certain throughput of wafers, and each wafer will have a certain number of ICs on it. Therefore, by making the individual devices of an IC smaller, more devices may be fabricated on each wafer, thus increasing the output of the fabrication facility. Making devices smaller is very challenging, as each process used in IC fabrication has a limit. That is to say, a given process typically only works down to a certain feature size, and then either the process or the device layout needs to be changed. An example of such a limit is the ability to reduce the size of a semiconductor device in a cost efficient and effective way.
Various techniques have been used to reduce the size of semiconductor devices. An example of such techniques includes the use of sidewall spacers on edges of metal oxide silicon (MOS) gate structures. Such sidewall spacers are used to form a self-aligned contact region, which is smaller in size and more efficient to manufacture. Other techniques use increasingly smaller gate structure, shallower implanting techniques, among others. Unfortunately, many limitations exist with the conventional semiconductor devices. The reduced cell size is based upon practical limits of processes and equipments used for the manufacture of semiconductor devices.
Please refer to FIG. 1, a cell of a conventional MOS gate structure having an active area 102 width of W. W is calculated as:W=L+2(S+C+E)  (1)where L is the minimum length for a gate polysilicon 104, S is the minimum distance between a contact open 106 and the gate polysilicon, C is the minimum contact length, and E is the minimum distance between the contact open and the edge of the active area.
From the equation 1, assuming L is the minimum resolution Rm, then from the design rules of various technologies based on conventional CMOS process, S+C is approximately 2 Rm, and E is approximately 0.5 Rm. Therefore, W is approximately 6 Rm.
For the forgoing reasons, there is a need for a new method of fabricating an IC wherein the device size may be significantly reduced without having to leverage upon pushing the expensive lithography further.